A subworld-parallel multiplication and sum-of-squares unit

Several recent digital signal processors, multimedia processors, and general-purpose processors with multimedia extensions support subword parallelism. With subword parallelism, each operand is partitioned into multiple lower-precision operands, called subwords. A single subword-parallel instruction performs the same operation on multiple sets of subwords in parallel. This paper presents the design of a subword-parallel multiplication and sum-of-squares unit (SPMSSU). The SPMSSU uses novel subword partitioning and partial product mapping techniques to perform one 32-bit, two 16-bit, or four 8-bit multiplications or sum-of-squares operations in parallel. The SPMSSU efficiently performs subword-parallel operations with area and delay estimates that are comparable to those of a conventional 32-bit multiplier.