An FPGA based system for discrete Hartley transforms

Discrete Hartley transforms (DHTs) are very important in many types of applications including image and signal processing. Two novel architectures for computing DHTs using both systolic architecture and distributed arithmetic design methodologies are presented. The first approach uses the Baugh-Wooley algorithm for a systolic architecture implementation. The second approach is based on distributed arithmetic read only memory (ROM), accumulator structure and offset binary coding (OBC) techniques. Implementations of the algorithms on a Xilinx FPGA are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.