A surface potential model for predicting substrate noise coupling in integrated circuits

In integrated circuits, it must be verified that noise injected and transmitted through the substrate does not degrade the performance of sensitive circuitry present on the chip. In this paper, we present a simple analytic substrate model for evaluating substrate noise coupling. The model handles an arbitrary number of aggressor and victim devices as well as biased and floating chip backside. The model has been validated by measurements on test structures manufactured in a 0.35 μm CMOS process, and it is shown that the model gives an accurate description of the substrate noise coupling. For example, the noise suppressing properties of guard rings have been evaluated.