DocumentCode
421340
Title
Facilitating reuse in hardware models with enhanced type inference
Author
Vachharajani, Manish ; Vachharajani, Neil ; Malik, Sharad ; August, David I.
Author_Institution
Dept. of Comput. Sci. & Electr. Eng., Princeton Univ., NJ, USA
fYear
2004
fDate
8-10 Sept. 2004
Firstpage
86
Lastpage
91
Abstract
High-level hardware modeling is an essential, yet time-consuming, part of system design. However, effective component-based reuse in hardware modeling languages can reduce model construction time and enable the exploration of more design alternatives, leading to better designs. While component overloading and parametric polymorphism are critical for effective component-base reuse, no existing modeling language supports both. The lack of these features creates overhead for designers that discourages reuse, negating any benefits of reuse. This work presents a type system which supports both component overloading and parametric polymorphism. It proves that performing type inference for any such system is NP-complete and presents a heuristic that works efficiently in practice. The result is a type system and type inference algorithm that can encourage reuse, reduce design specification time, and lead to better designs.
Keywords
computational complexity; hardware description languages; high level synthesis; polymorphism; type theory; NP-completeness; component overloading; component-based reuse; design specification; hardware modeling languages; high-level hardware modeling; liberty simulation environment; parametric polymorphism; system design; type inference algorithm; Algorithm design and analysis; Buildings; Computer languages; Computer science; Concrete; Hardware; Inference algorithms; Lead time reduction; Permission; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. International Conference on
Print_ISBN
1-58113-937-3
Type
conf
DOI
10.1109/CODESS.2004.240823
Filename
1360486
Link To Document