Will the ASIC survive?

ASIC design starts have declined lately and many voices speak of fundamental changes as a result of increasing design costs, predicting even the extinction of ASIC design altogether. ASICs and ASSPs have been a formidable economic force, accounting for over one third of the semiconductor market. Standard cell based designs have also been the major consumer of EDA tools and design technology. However, raising NRE costs which stand at approximately $10 M to design an ASIC at the 130 nm technology node, cost of re-spins, lack of flexibility (compared to programmable solutions) and increasing time to market have prompted the search for other design styles. These include structured ASICs, FPGAs, processor arrays and "platforms", which are all trying to fill the void left by the slowing of ASIC design starts. The reality however is that none has so far proven to be a solution with a wide spectrum of applications, because they are either a limited economic choice or because their performance constraints the application space. This presentation addresses the trade-offs among these design solutions and also looks at several ways of mixing these technologies. These alternative solutions are reviving cell-based design by adding the flexibility of those alternative solutions to the traditional ASIC design.