A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 μm CMOS technology

Author

De Miranda, Fernando P H ; Navarro, S.J. ; Van Noije, Wilhelmus A M

Author_Institution

Escola Politecnica, Sao Paulo Univ., Brazil

fYear

2004

fDate

7-11 Sept. 2004

Firstpage

94

Lastpage

99

Abstract

The design of a dual modulus prescaler 32/33 in a 0.35 μm CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.

Keywords

CMOS digital integrated circuits; frequency dividers; frequency synthesizers; high-speed integrated circuits; integrated circuit layout; low-power electronics; prescalers; 0.35 micron; 3.3 V; 32/33 prescaler; 4 GHz; 4.38 mW; CMOS technology; dual modulus divider; extended true single phase clock technique; high frequency synthesizer designs; high speed integrated circuits; integrated circuit layout; low-power electronics; power consumption; CMOS technology; Circuit simulation; Clocks; Counting circuits; Energy consumption; Frequency synthesizers; Integrated circuit technology; Permission; Power supplies; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on

Print_ISBN

1-58113-947-0

Type

conf

DOI

10.1109/SBCCI.2004.241286

Filename

1360551