When reconfigurable architecture meets network-on-chip

Author

Soares, Rodrigo ; Silva, I.S. ; Azevedo, SilvaArnaldo

Author_Institution

DIMAP, Univ. Fed. do Rio Grande do Norte, Natal, Brazil

fYear

2004

fDate

7-11 Sept. 2004

Firstpage

216

Lastpage

221

Abstract

This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and simulated using coarse-grained reconfigurable microprocessor as processing nodes. To perform the simulation two approaches were used. The first one uses a load generator program and communication loads between 5% and 25%. The second is the calculation of 2D-DCT coefficients.

Keywords

discrete cosine transforms; integrated circuit design; microprocessor chips; parallel architectures; reconfigurable architectures; system-on-chip; 2D-DCT coefficients; NoCX4; SystemC; coarse grained reconfigurable microprocessor; communication subsystem; load generator program; network-on-chip; parallel architecture; processing nodes; reconfigurable architecture; router architecture; Field programmable gate arrays; Manufacturing industries; Microprocessors; Network-on-a-chip; Permission; Productivity; Reconfigurable architectures; Semiconductor device measurement; System-on-a-chip; Telecommunication network reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on

Print_ISBN

1-58113-947-0

Type

conf

DOI

10.1109/SBCCI.2004.240878

Filename

1360572