High-Gain and Linear 60-GHz Power Amplifier With a Thin Digital 65-nm CMOS Technology

The analysis and optimization of millimeter-wave coupling structures are detailed to design a high-performance V-band 65-nm CMOS parallel power amplifier (PA). The difficulty in this design consists of the use of a thin digital seven metal layer, back end of line, and low-power transistors dedicated to pure digital applications. In this context, two transformer-based power-combining schemes are compared using a lumped model analysis. A distributed active transformer with a mixed current-voltage mode is then proposed for power combination. Furthermore, baluns and 0° 1-4 splitters are codesigned and implemented in the design. Two PAs are fabricated and measured. The first PA represents the power stage of the high-gain linear PA. At 61 GHz, the PA achieves a peak power gain of 20 dB with a 13.5-dBm 1-dB output compression point (OCP_1dB) . It produces 15.6-dBm saturated power and a power-added efficiency of 6.6% from a 1.2-V supply. Finally, experimental measurements of the temperature distribution in the CMOS PA chip are illustrated and analyzed. To the authors´ knowledge, these results represent the highest linear output power and gain performances among PAs using the same digital technology.