An efficient computational method and a VLSI architecture for digital filtering of CP-OFDM signals

This paper introduces an efficient computational technique for orthogonal frequency division multiplexing (OFDM) based modem design with digital filters and discusses the corresponding VLSI architecture issues. General conditions are introduced, under which the proposed technique is applicable. The proposed technique is demonstrated by detailing the implementation of a 64-point, radix-4 pipelined FFT in combination with a parallel digital filter architecture. By exploiting the redundancy into the cyclic prefix part of the OFDM symbol, the computational load of the transmitter is reduced by 20% for cases of practical interest. The radix-r N-point FFT case is examined.