• DocumentCode
    42380
  • Title

    Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems

  • Author

    Clemente, J.A. ; Perez Ramo, Elena ; Resano, Javier ; Mozos, Daniel ; Catthoor, Francky

  • Author_Institution
    Comput. Archit. Dept., Univ. Complutense de Madrid, Madrid, Spain
  • Volume
    22
  • Issue
    6
  • fYear
    2014
  • fDate
    Jun-14
  • Firstpage
    1248
  • Lastpage
    1261
  • Abstract
    In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can introduce important overheads, both in terms of energy consumption and time, especially when configurations are fetched from an external memory. To address this problem, this paper presents a configuration memory hierarchy including two on-chip memory modules with different access time and energy consumption features. In addition, we have developed two configuration mapping algorithms that take advantage of these memories to reduce the system energy consumption, while increasing its performance. The first algorithm has been optimized for systems with reduced dynamic behavior; hence it optimizes the system for each given set of tasks. The second algorithm targets dynamic systems where the active tasks change unpredictably. Thus, its objective is also to decrease the pressure on the on-chip memories to reduce capacity conflicts. The presented results will demonstrate that, with the proper management, our configuration memory hierarchy leads to an energy consumption reduction up to 81% with respect to fetching the configurations from the external memory, while keeping the system performance very close to the ideal upper-bound one.
  • Keywords
    configuration management; energy conservation; field programmable gate arrays; power aware computing; storage management; capacity conflicts reduction; configuration mapping algorithms; configuration memory hierarchy; dynamic reconfiguration; energy reconfiguration overheads; field programmable gate arrays; on-chip memory modules; overhead reduction; reconfigurable hardware; reconfigurable systems; time reconfiguration overheads; Delays; Energy consumption; Field programmable gate arrays; Hardware; Heuristic algorithms; Memory management; System-on-chip; Configuration energy consumption; configuration mapping; configuration time overheads; field-programmable gate array (FPGA); field-programmable gate array (FPGA).;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2013.2271917
  • Filename
    6623203