DocumentCode :
423951
Title :
Vertically-integrated photonic multichip module architecture for vision applications
Author :
Tanguay, A.R., Jr. ; Jenkins, B.K. ; von der Malsburg, C. ; Mel, B. ; O´Brien, J. ; Biederman, I. ; Madhukar, A.
Volume :
3
fYear :
2004
fDate :
25-29 July 2004
Abstract :
Adaptive vision applications that involve rapid object identification and moving object tracking, such as in envisioned augmented reality applications, increasingly place stringent upper bounds on processing latency. In addition to the requirement for low latency, many emerging vision models and algorithms involves operations that are parallel in nature, nonlinear in functionality, and both local and non-local in structure. The resulting computational complexity places correspondingly complex demands on envisioned hardware implementations. In order to satisfy these conjoint requirements, a hybrid electronic/photonic multichip module architecture that comprises multiple layers of silicon VLSI detection and processing circuitry, coupled in the vertical dimension with dense photonic fan-out/fan-in interconnections has been investigated. The interconnections are implemented by means of 2D arrays of either multiple quantum well modulators or VCSEL that are flip-chip bonded on a pixel-by-pixel basis to the silicon VLSI detector/processor array.
Keywords :
VLSI; augmented reality; computational complexity; computer vision; flip-chip devices; integrated optoelectronics; multichip modules; quantum well devices; surface emitting lasers; VCSEL; adaptive vision applications; computational complexity; envisioned augmented reality; flip chip devices; hybrid electronic multichip module; latency processing; moving object tracking; multiple quantum well modulators; photonic fan-in interconnections; photonic fan-out interconnections; photonic multichip module architecture; rapid object identification; silicon VLSI detection; silicon VLSI processing circuitry; stringent upper bounds; vertically integrated photonic multichip; Augmented reality; Computational complexity; Delay; Hardware; Integrated circuit interconnections; Multichip modules; Sensor arrays; Silicon; Upper bound; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on
ISSN :
1098-7576
Print_ISBN :
0-7803-8359-1
Type :
conf
DOI :
10.1109/IJCNN.2004.1380869
Filename :
1380869
Link To Document :
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