Title :
Implementation of a large scale hardware neural network system based on stochastic logic
Author :
Momoi, Akiyoshi ; Akimoto, Shunsuke ; Sato, Shigeo ; Nakajima, Koji
Author_Institution :
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
Abstract :
We present a large scale hardware neural network system which consists of 16 chips, 1024 neurons. The system is realized by using stochastic logic. Stochastic logic makes possible to implement numerous neurons on a VLSI chip and to build a system comprising multiple chips easily. In addition, stochastic logic has a characteristic as some noise is generated while coding operations. This noise is effective for escaping from the local minima in a Hopfield network. The availability of this noise is confirmed in the measurement of our system.
Keywords :
VLSI; neural net architecture; neural nets; stochastic processes; Hopfield network; VLSI chip; large scale hardware neural network system; stochastic logic; Character generation; Large-scale systems; Logic; Neural network hardware; Neural networks; Neurons; Noise generators; Stochastic resonance; Stochastic systems; Very large scale integration;
Conference_Titel :
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on
Print_ISBN :
0-7803-8359-1
DOI :
10.1109/IJCNN.2004.1381070
