Title :
Low-Power Fixed-Width Array Multipliers
Author :
Jinn-Shyan Wang ; Chien-Nan Kuo ; Tsung-Han Yang
Author_Institution :
Chung-Cheng University, Taiwan
Abstract :
A fixed-width multiplier using the left-to-right algorithm for partial-product reduction is presented. The high-speed feature offered by this design is used to trade for low power. In one design, the proposed multiplier not only owns 8% speed improvement but also gains 14% power and 13% area reduction. When applying the voltage scaling to balance the speed, the power reduction is increased to 29%.
Keywords :
Left-to-right multiplier; fixed-width multiplier; low power; reduced-width multiplier; Left-to-right multiplier; fixed-width multiplier; low power; reduced-width multiplier;
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Conference_Location :
Newport Beach, CA, USA
Print_ISBN :
1-58113-929-2
