DocumentCode :
424527
Title :
VLSI design challenges for gigascale integration
Author :
Borkar, Shekhar
fYear :
2005
fDate :
3-7 Jan. 2005
Firstpage :
27
Abstract :
VLSI system performance increased by five orders of magnitude in the last three decades, made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill will continue, providing integration capacity of billions of transistors; however, power and energy consumption will be the barriers. Performance at any cost will not be an option in the future; VLSI systems will have to emphasize performance delivered in a given power envelope, with complexity limited by energy efficiency. This paper discusses potential solutions in process technology, circuits, and microarchitectures to exploit future gigascale integration capacity. The system on a chip (SOC) concept will help integrate diverse functional blocks, providing valued performance. The paper concludes with recommendations to the VLSI system designers on how to exploit these emerging paradigms.
Keywords :
VLSI; circuit complexity; integrated circuit design; logic design; system-on-chip; VLSI design challenges; diverse functional block integration; energy consumption; gigascale integration; power consumption; system on a chip concept; Circuits; Costs; Energy consumption; Energy efficiency; Frequency; Logic; Microarchitecture; Power dissipation; System performance; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2264-5
Type :
conf
DOI :
10.1109/ICVD.2005.171
Filename :
1383246
Link To Document :
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