Evaluation of device parameters of HfO2/SiO2/Si gate dielectric stack for MOSFETs

Among the potential candidates for replacement of SiO₂ or SiO_xN_y as gate dielectric, HfO₂ seems to be one of the most promising materials, combining high dielectric permittivity with low leakage current due to a reasonably high barrier height that limits electron tunneling (Peacock and Robertson, 2004). Other requirements on gate dielectric materials like low density of interface states, gate compatibility, structural, physical and chemical stability at both gate electrode/dielectric and dielectric/silicon interfaces are currently making the object of intensive investigation for sub 0.1 μm channel length devices using high-k dielectrics. The transition layer becomes important in such dielectrics in deciding the device performance. In this paper, we discuss the scaling limits of HfO₂/SiO₂ stacked dielectrics taking into consideration the impact of transition layer between HfO₂ and SiO₂. In this paper, analysis of HfO₂/SiO₂ gate dielectric stack has been carried out for replacement of SiO₂ using an appropriate direct-tunneling gate-current model. It has the potential to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies.