A technique for throughput and register optimization during resource constrained pipelined scheduling

This paper presents a novel method for resource constrained and registers aware pipelined scheduling of data flow graphs. In a VLSI circuit, it is essential to minimize area, and to obtain a schedule that requires as few registers as possible. A technique that combines path-based scheduling algorithm and retiming heuristic has been developed to produce a schedule with maximum throughput while minimizing the register requirement. The effectiveness of the proposed technique is demonstrated by experimentation with several representative high level synthesis benchmarks and loop kernels. It is observed that our technique produces an average of 22.76% reduction in register requirements in comparison with rotation scheduling as stated in L.-F. Chao et al. (1993) when a bottom-up scheduling method is used. For the top-down scheduling case the technique produces an average reduction of 20.22% in register requirements.