DocumentCode :
424536
Title :
Computer aided test (CAT) tool for mixed signal SOCs
Author :
Banerjee, Shibaji ; Mukhopadhyay, Debdeep ; Chowdhury, Dipanwita Roy
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
fYear :
2005
fDate :
3-7 Jan. 2005
Firstpage :
787
Lastpage :
790
Abstract :
This paper introduces a computer-aided-test (CAT) tool for mixed signal SOC designs. A new DFT strategy has been developed to make the testing scheme digitally compliant. The final DFT solution is generated through scheduling algorithms. The mixed signal cores have been accessed through specially design mechanisms (switches). Extensive experiments have been performed on Mixed Signal SOC benchmarks built of ISCAS´89 circuits for digital cores and ITC ´97 circuits for analog cores. Results show that the CAT tool provides a hardware efficient integrated DFT solution.
Keywords :
circuit CAD; design for testability; integrated circuit testing; mixed analogue-digital integrated circuits; scheduling; system-on-chip; CAT tool; DFT solution; ISCAS´89 circuits; ITC ´97 circuits; SOC design; analog core; computer aided test; digital core; digital testing; mixed signal SOC; scheduling algorithm; switches; Benchmark testing; Circuit testing; Computer science; Design for testability; Hardware; Scheduling algorithm; Signal design; Silicon compounds; Switches; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2264-5
Type :
conf
DOI :
10.1109/ICVD.2005.67
Filename :
1383370
Link To Document :
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