Realizing high test quality goals with smart test resource usage

Author

Gu, Xinli ; Wang, Cyndee ; Lee, Abby ; Eklow, Bill ; Tsai, Kun-Han ; Tofte, Jan A. ; Kassab, Mark ; Rajski, Janusz

Author_Institution

Cisco Syst. Inc., San Jose, CA, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

525

Lastpage

533

Abstract

Growing ASIC design sizes and advanced deep sub-micron technologies require new fault models and more test vectors to meet high test quality goals. To realize these goals within given test resources and cost constraints, new DFT techniques must be used. This paper reports test quality metrics and the test cost of industrial designs for different fault models using three DFT techniques: ATPG for deterministic patterns, Logic BIST for pseudo-random patterns, and EDT for compressed deterministic patterns. It is shown how these techniques can be used to achieve the high quality goals within the test resources currently available for stuck-at tests.

Keywords

application specific integrated circuits; automatic test pattern generation; built-in self test; design for testability; fault diagnosis; integrated circuit testing; logic testing; ASIC design sizes; ATPG; DFT techniques; advanced deep submicron technology; compressed deterministic patterns; cost constraints; embedded deterministic test; fault models; high test quality; industrial designs; logic BIST; pseudorandom patterns; smart test resource usage; stuck at tests; test quality metrics; test vectors; Application specific integrated circuits; Automatic testing; Delay; Design for testability; Geometry; Logic testing; Solid modeling; System testing; Test pattern generators; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1386989

Filename

1386989