Automatic delay calibration method for multi-channel CMOS formatter

Author

Syed, Ahmed Rashid

Author_Institution

Credence Syst. Corp., San Jose, CA, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

577

Lastpage

586

Abstract

This work describes the technique used for automatically calibrating vernier delay steps in Credence CMOS formatter-RIC/DICMOS. Embedded within the timing generation IC, RIC/DICMOS provides formatted levels and internal strobe markers for eight independent pin-electronics channels at up to 800 Mbps with +/-81 ps accuracy. Utilizing the on-chip, run-time auto-calibration circuit, all eight RIC/DICMOS vernier channels can be calibrated in parallel nearly 500 times faster than the prior generation formatters. Furthermore, the same calibration circuit can also provide 16-bit time-period or frequency counts for up to eight independent off-chip signals.

Keywords

CMOS integrated circuits; calibration; system-on-chip; timing circuits; 0 to 800 Mbit/s; Credence CMOS formatter; RIC/DICMOS vernier channels; automatic delay calibration method; independent off-chip signals; independent pin electronics channels; internal strobe markers; multichannel CMOS formatter; prior generation formatters; run time autocalibration circuit; system on chip; timing generation IC; CMOS process; Calibration; Circuit testing; Cost function; Delay; Design engineering; Pins; Runtime; Systems engineering and theory; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1386995

Filename

1386995