DocumentCode :
425724
Title :
ALAPTF: a new transition fault model and the ATPG algorithm
Author :
Gupta, Puneet ; Hsiao, Michael S.
Author_Institution :
Cadence Design Syst., Endicott, NY, USA
fYear :
2004
fDate :
26-28 Oct. 2004
Firstpage :
1053
Lastpage :
1060
Abstract :
The work presents a new transition fault model called as late as possible transition fault (ALAPTF) model. The model aims at detecting smaller delays, which be missed by both the traditional transition fault model and the path delay model. The model makes sure that each transition is launched as late as possible at the fault site, accumulating the small delay defects along its way. Because some transition faults may require multiple paths to be launched, the simple path-delay model miss such faults. Results on ISCAS´85 and ISCAS´89 benchmark circuits shows that for all the cases, the new model is capable of detecting smaller gate delays and produces better results in case of process variations. For all circuits, on an average, 30% of the time the transition reaches later than traditional models. The algorithm proposed also detects robust and non-robust paths along with the transition faults and the execution time is linear to the circuit size.
Keywords :
automatic test pattern generation; delays; fault diagnosis; integrated circuit testing; ATPG algorithm; ISCAS85 benchmark circuits; ISCAS89 benchmark circuits; as late as possible transition fault model; delay defects; gate delay detection; linear execution time; nonrobust path detection; path delay model; robust path detection; Automatic test pattern generation; Circuit faults; Circuit testing; Delay effects; Electrical fault detection; Engines; Fault detection; Resists; Robustness; Tellurium;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
Type :
conf
DOI :
10.1109/TEST.2004.1387378
Filename :
1387378
Link To Document :
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