Implementation of an economic jitter compliance test for a multi-gigabit device on ATE

State of the art communication devices combine multiple high-speed interfaces like SFI4.2 and XAUI with speeds up to 3.2 gigabits per second (Gbps) on a single CMOS chip. One key parameter common to the specification of these interfaces is the jitter observed on the transmitters. Existing automated test approaches are not able to cover this parameter during production test at a reasonable economical performance, determined by the following items: capital investment, time-to-market (TTM) and test cost per chip. This work includes a discussion of the need for jitter separation, a thorough review of jitter separation algorithms and also presents the results of a specific jitter separation approach with an at-speed ATE system.