DocumentCode :
425740
Title :
Panel 7 : cost of test - taking control [failure mechanism]
Author :
Mukherjee, Nandini
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
fYear :
2004
fDate :
26-28 Oct. 2004
Firstpage :
1431
Abstract :
Nanometer technology have not only resulted in increasingly complex chips but is also exposing new defects and failure mechanisms during manufacturing that are challenging process and test engineers while they struggle to maintain high yield and low DPM. Silicon manufacturers are increasingly using structural test vectors to improve the process and consequently, reduce the defect rates. Structural vectors help detect defective parts and debug issues in an automated manner, which subsequently allows ramping up the yield for a given process fairly quickly. In addition, it reduces the number of escaped parts thereby guaranteeing lower DPM and fewer field returns. However, relying more on structural tests implies that the test set should be of the highest quality and may include vectors for fault models (in addition to stuck-at faults) such as transition, path-delay, bridging, n-detect, in-line resistance, Iddq, etc., covering some of the new failure mechanisms.
Keywords :
failure analysis; fault diagnosis; nanotechnology; defect rate reduction; defects per million; failure mechanisms; fault models; nanometer technology; silicon manufacturers; structural test vectors; stuck-at faults; Costs; Electronics industry; Failure analysis; Graphics; Logic testing; Maintenance engineering; Manufacturing processes; Semiconductor device testing; Silicon; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
Type :
conf
DOI :
10.1109/TEST.2004.1387439
Filename :
1387439
Link To Document :
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