Memory yield improvement - SoC design perspective

On-chip memories are a major source of yield loss in SoC designs. Currently, redundancy is the only available option to improve memory yield. However, other techniques - e.g., DFM-based bit-cell design, flexibility in bit-cell choice, and ability to choose the number of metal layers - can be more effective. The availability of such techniques allow designers to tailor memories to the specific SoC architecture. Such strategies reduce die cost, but require close collaboration between the foundry, IP companies and customers.