Design space exploration of HSDPA subsystem algorithms and architectures

A new transport channel type was introduced in 3GPP to support high-speed data packet access (HSDPA). It makes efficient use of valuable radio frequency resources. More flexibility and resource sharing leads to more control. A separate shared control channel (HS-SCCH) is defined to carry convolutionally encoded control data over the air interface to allow for fast adaptation to system dynamics. Thus, low-latency HS-SCCH subsystems are key building blocks impacting major design choices of the underlying HSDPA architecture. We systematically analyze different algorithm and architecture candidates at various levels of abstractions. At the functional level, formalizing the complexity, i.e. operations, memory size and access rate, we show how algorithm and architecture transformations of the classical max-log-MAP and Viterbi algorithm are traded-off with communication performance. At the architecture level, DSP implementation strategies are discussed. Cycle estimates are presented for two STMicroelectronics DSP platforms - the ST122 and a small, application-specific DSP. Finally, we propose a low-latency, energy-efficient software implementation of HS-SCCH decoding referred to as short-sequence Viterbi-like approach.