Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication

Author

McLoone, Maire ; McIvor, C. ; McCanny, John V.

Author_Institution

Inst. of Electron., Commun. & Inf. Technol., Queen´´s Univ. Belfast, UK

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

185

Lastpage

191

Abstract

A generic coarsely integrated operand scanning (CIOS) architecture that provides high speed Montgomery modular multiplication is presented in This work. The architecture is capable of supporting varying operand sizes. It achieves a throughput of 210 Mbps, 289 Mbps and 334 Mbps for 128-bit, 256-bit and 512-bit operand sizes respectively, when implemented on a Virtex XC2 VP50 FPGA. Throughputs of up to 400 Mbps are achieved if the final subtraction in the Montgomery algorithm is excluded. To the authors´ knowledge this is the fastest Montgomery multiplication architecture reported in the literature.

Keywords

digital arithmetic; field programmable gate arrays; high-speed integrated circuits; logic design; multiplying circuits; 128 bit; 210 Mbit/s; 256 bit; 289 Mbit/s; 334 Mbit/s; 512 bit; CIOS architecture; Virtex XC2 VP50 FPGA; coarsely integrated operand scanning; high-speed Montgomery modular multiplication; operand sizes; Data security; Digital signatures; Elliptic curve cryptography; Field programmable gate arrays; Hardware; Information technology; Protocols; Public key; Software performance; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Print_ISBN

0-7803-8651-5

Type

conf

DOI

10.1109/FPT.2004.1393267

Filename

1393267