A scalable and pipelined FPGA implementation of an OC192 WF scheduler

Author

Merhebi, A. ; Mohamed, O. Lit

Author_Institution

Dept. of ECE, Concordia Univ., Montreal, Que., Canada

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

395

Lastpage

398

Abstract

We propose an FPGA implementation of a multi protocol weighted fair (WF) queuing algorithm able to handle variable length packets targeted for POS interfaces and ideal for the design of hybrid IP/ATM switches. Our contributions are two folds: first, we have combined the Highest Value First scheme and the Round Robin scheme into a single pipelined design able to schedule traffic for 4 channels in parallel. Second, we showed how to build higher order WF queuing system without decreasing the overall performance of our scheduler. As a result, our scheduler is general enough to accommodate ATM (UTOPIA L3/L4) , POS/PL3 (OC48) as well as POS/PL4 (OC192) interfaces.

Keywords

asynchronous transfer mode; field programmable gate arrays; pipeline processing; protocols; queueing theory; telecommunication traffic; ATM interface; OC192 WF scheduler; OC192 interface; OC48 interface; POS interfaces; POS/PL3 interface; POS/PL4 interface; UTOPIA L3/L4 interface; WF queuing system; field programmable gate arrays; highest value first scheme; hybrid IP/ATM switch; multiprotocol weighted fair queuing algorithm; pipelined FPGA implementation; round robin scheme; scalable FPGA implementation; single pipelined design; traffic scheduling; variable length packets; Asynchronous transfer mode; Field programmable gate arrays; Protocols; Round robin; SONET; Scheduling; Streaming media; Switches; Telecommunication traffic; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Print_ISBN

0-7803-8651-5

Type

conf

DOI

10.1109/FPT.2004.1393308

Filename

1393308