PT-LRU: a probabilistic page replacement algorithm for NAND flash-based consumer electronics

The flash memory is being used to an everincreasing extent in consumer electronics for the purpose of the dominant secondary storage device. Aiming at the buffer replacement policy for flash-based storage devices in efficiency, a new efficient flash-aware buffer replacement algorithm based on probability is proposed, where three LRU linked lists are used to manage the buffer. The proposed algorithm delays the eviction of hot clean pages by evicting the cold clean pages preferentially. When the cold clean linked list is empty, the pages in the cold dirty linked list will be expelled from the buffer with a higher probability, whereas the probability of evicting the hot clean pages is lower. In that way, hot clean pages cannot reside in the buffer for a long time. Moreover, an interpretation model for describing the proposed algorithm is developed from FSM. Highlights of the experiments include an evaluation with the dynamic write/read ratio traces. Experimental results and detailed comparisons with other similar best-known competitor algorithms on the static write/read ratio traces and the dynamic write/read ratio traces show that not only does the proposed algorithm reduce the write counts, but also it offers a trade-off between the hit ratio and the overall runtime in most cases. The adaptability of the proposed method is also verified by the experiments on various kinds of traces including random, read-most, write-most and Zipf.