Title :
Substrate design optimization for high performance small form factor flip chip ball grid array (FCBGA) packages
Author :
Yoon, C.K. ; Landeros, J. ; Goh, H.S. ; Teh, Alan ; Chee, Joseph ; Loke, C.C. ; Mahadevan, S.
Author_Institution :
Intel Technol. (M) Sdn Bhd, Penang, Malaysia
Abstract :
This work summarizes the multiple design and development activities within Intel to optimize the real estate for FCBGA packaging technology. The advantages made are part of the cost saving solutions to enable high performance small form factor flip chip ball grid array (FCBGA) substrate. Key focus areas include challenges in enabling ultra mini 0402/0201 die side capacitor (DSC), optimizing transfer media or material handling system, optimizing assembly and test tooling design for smaller and cheaper substrate design.
Keywords :
ball grid arrays; chip scale packaging; flip-chip devices; integrated circuit design; optimisation; substrates; FCBGA packaging technology; assembly optimization; die side capacitor; flip chip ball grid array; form factor; material handling system; substrate design optimization; test tooling design; transfer media; Assembly; Capacitors; Computers; Costs; Design optimization; Electronics packaging; Flip chip; Printing; Silicon; Testing;
Conference_Titel :
Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th
Print_ISBN :
0-7803-8821-6
DOI :
10.1109/EPTC.2004.1396635
