DocumentCode
42761
Title
Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm
Author
Ancajas, Dean Michael ; Bhardwaj, Kshitij ; Chakraborty, Koushik ; Roy, Sanghamitra
Author_Institution
Dept. of Electr. & Comput. Eng., Utah State Univ., Logan, UT, USA
Volume
23
Issue
2
fYear
2015
fDate
Feb. 2015
Firstpage
369
Lastpage
373
Abstract
Continuous technology scaling has made aging mechanisms, such as negative bias temperature instability and electromigration primary concerns in network-on-chip (NoC) designs. In this paper, we extensively analyze the effects of these aging mechanisms on NoC routers and links. We observe a critical need of a robust aging-aware routing algorithm that not only reduces power-performance overheads caused due to aging degradation, but also minimizes the stress experienced by heavily utilized routers and links. To solve this problem, we propose an aging-aware adaptive routing algorithm and a router microarchitecture that routes the packets along the paths, which are both least congested and experience minimum aging degradation. After an extensive experimental analysis using real workloads, we observe 13% and 12.17% average overhead reduction in network latency and energy-delay product per flit, a 10.4% improvement in performance, and a 60% improvement in mean time to failure using our aging-aware routing algorithm.
Keywords
negative bias temperature instability; network routing; network-on-chip; NoC; aging aware adaptive routing algorithm; continuous technology scaling; negative bias temperature instability; network-on-chip; router microarchitecture; wearout resilience; Aging; Algorithm design and analysis; Circuit faults; Degradation; Delays; Fault tolerance; Routing; Multicore processing; multiprocessor interconnection networks; parallel architecture; parallel architecture.;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2014.2305335
Filename
6775326
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