DocumentCode
427709
Title
Sparse-coefficient polynomial approximations for hardware implementations
Author
Brisebarre, Nicolas ; Muller, Jean-Michel ; Tisserand, Arnaud
Author_Institution
Lab. de l´´Informatique du Parallelisme, Ecole Normale Superieure de Lyon, France
Volume
1
fYear
2004
fDate
7-10 Nov. 2004
Firstpage
532
Abstract
This paper presents a method for automatic generation of best polynomial approximations dedicated to hardware implementation. The generated polynomial approximations lead to high-speed and small hardware operators because of the use of sparse coefficients (i.e. we include fixed strings of zeros in the binary representation of the coefficients). Two different solutions have been investigated for the generation of the sparse-coefficient polynomial approximations. Our first results show up to 47% smaller coefficients compared to standard minimax approximations for comparable accuracy.
Keywords
multiplying circuits; polynomial approximation; sparse matrices; hardware implementation; hardware operator; polynomial approximation; sparse coefficient; Approximation algorithms; Demodulation; Digital signal processing; Digital systems; Electronic mail; Frequency; Hardware; Minimax techniques; Polynomials; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on
Print_ISBN
0-7803-8622-1
Type
conf
DOI
10.1109/ACSSC.2004.1399189
Filename
1399189
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