Implementation of an LDPC decoder on a vector signal processor

Author

Lechner, Gottfried ; Bolzer, Andreas ; Sayir, Jossy ; Rupp, Markus

Author_Institution

Telecommun. Res. Center Vienna, Austria

Volume

1

fYear

2004

fDate

7-10 Nov. 2004

Firstpage

549

Abstract

A parallel processor architecture-a vector signal processor (VSP), which consists of independent computation units is presented. This architecture is used to implement the sum-product algorithm to decode low-density parity-check codes. The VSP is well suited for this parallel decoding algorithm which results in a scalable decoder that allows a tradeoff between chip area and data throughput. With increasing number of computation units a data throughput of up to 36.1 MBit per second can be achieved which outperforms existing implementations on digital signal processors.

Keywords

decoding; digital signal processing chips; parallel algorithms; parallel architectures; parity check codes; vector processor systems; VSP; chip area; digital signal processor; low-density parity-check code; parallel decoding algorithm; parallel processor architecture; sum-product algorithm; vector signal processor; Arithmetic; Computer architecture; Decoding; Parity check codes; RF signals; Registers; Signal processing; Signal processing algorithms; Throughput; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on

Print_ISBN

0-7803-8622-1

Type

conf

DOI

10.1109/ACSSC.2004.1399193

Filename

1399193