Two ESD Detection Circuits for 3x VDD-Tolerant I/O Buffer in Low-Voltage CMOS Processes With Low Leakage Currents

Two novel 3×VDD-tolerant electrostatic discharge (ESD) protection circuits using only low-voltage devices without extra power consumption are proposed for 0.18- μm 1.8-V and 90-nm 1.2-V CMOS processes, respectively. Stacked-capacitor technique and bias circuit are adopted in the two designs. The proposed ESD detection circuits can generate 36- and 38-mA currents to trigger the ESD clamp device under the ESD event. Under normal operating conditions, all the devices are free from the gate-oxide reliability threat. The leakage currents of the 0.18- μm and 90-nm circuits are 0.9 and 200 nA under 3×VDD, respectively. The simulation results show that both the circuits can be successfully used for 3×VDD-tolerant I/O buffers.