Design and VLSI implementation of WCDMA coding layer

This paper presents a hardware-centric implementation of the symbol level processing for the WCDMA downlink. The presented architecture allows much lower power consumption than a traditional DSP-centric approach. The symbol level decoding blocks include: power control bit extraction, control/data separation, data scaling and quantization, 2^nd deinterleaving. The system-level architecture, including the interfacing of the hardware blocks to the μP and the memory sizing, is described and justified. The system includes intelligent bus arbitration to allow single-port memory to be used for all data storage.