Design of a dual-loop frequency synthesizer

Author

Sinha, Saurabh ; du Plessis, M.

Author_Institution

Dept. of Electr., Electron. & Comput. Eng., Pretoria Univ.

Volume

1

fYear

2004

fDate

17-17 Sept. 2004

Firstpage

525

Abstract

Due to higher costs, bulkiness and larger power consumption, it is no longer desirable to implement wireless transceivers with discrete elements. The paper describes the design of an essential component in wireless transceivers, the frequency synthesizer. The synthesizer is implemented using the dual phase locked loop (PLL) architecture. The synthesizer generates signals in the 2.4-2.5 GHz range with a 1 MHz resolution. Using the 0.35 mum CMOS process, post-layout simulations showed a phase noise of -82 dBc/Hz at an offset of 10 kHz and reference sidebands at -60 dBc, both these parameters with respect to a 2.45 GHz carrier

Keywords

CMOS analogue integrated circuits; circuit simulation; frequency synthesizers; integrated circuit design; phase locked loops; phase noise; transceivers; 0.35 micron; 2.4 to 2.5 GHz; CMOS process; PLL; dual phase locked loop; dual-loop frequency synthesizer; phase noise; power consumption; wireless transceivers; CMOS process; CMOS technology; Frequency synthesizers; Phase locked loops; Phase noise; Signal generators; Signal resolution; Transceivers; Voltage-controlled oscillators; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

AFRICON, 2004. 7th AFRICON Conference in Africa

Conference_Location

Gaborone

Print_ISBN

0-7803-8605-1

Type

conf

DOI

10.1109/AFRICON.2004.1406732

Filename

1406732