DocumentCode :
430122
Title :
Power delivery modeling and design methodology for a programmable logic device package
Author :
Pannikkat, Anil ; Long, Jon ; Zhao, Jin
Author_Institution :
Altera Corp., San Jose, CA, USA
fYear :
2004
fDate :
25-27 Oct. 2004
Firstpage :
115
Lastpage :
118
Abstract :
A power delivery modeling and design methodology for a programmable logic device package is presented in this paper. Both the DC IR drop and high frequency power ground input impedance have been analyzed by commercial available power integrity software and calibrated with measurements. Design modifications have then been carried out for power delivery system improvement of the package for next generation products.
Keywords :
electric impedance; electronics packaging; power engineering computing; power system simulation; programmable logic devices; DC IR drop; calibration; high frequency power ground input impedance; power delivery design methodology; power delivery modeling methodology; power delivery system; power integrity software; programmable logic device package; Circuit noise; Design methodology; Frequency; Impedance; Integrated circuit packaging; Performance analysis; Power supplies; Power system modeling; Programmable logic devices; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2004. IEEE 13th Topical Meeting on
Print_ISBN :
0-7803-8667-1
Type :
conf
DOI :
10.1109/EPEP.2004.1407561
Filename :
1407561
Link To Document :
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