A robust physical model extraction method for a memory device with differential routed package traces

To quantify the impact of device parasitics on the performance and yield of high-speed systems, a reliable procedure for parasitic extraction and characterization needs to be established. A robust physical model extraction method of silicon parasitic is developed for a 3.2 Gbps memory device with differentially routed package traces. This method employs parasitic models that directly correlate to the physical features in the PCB, fixture, package, and the active device under proper voltage biases. Measurements are performed using a vector network analyzer (VNA) and a differential time-domain reflectometry (TDR). The standard two-port S-parameters are converted to the mixed-mode S-parameters, i.e., odd and even mode S-parameters. The model parameters of the parasitics are then extracted through the minimization of the difference between the simulated and the measured odd-mode S-parameters. Measured TDR results, such as package impedance and on-die termination resistance, are used to constrain the variables and optimization range. This method is applied to the parasitic extraction of an actual device to demonstrate its accuracy and robustness.