DocumentCode
430127
Title
IBM Power5 bus designs for on- and off-module connections
Author
Dreps, D. ; Ferraiolo, F. ; Haridass, A. ; Reese, R. ; Schiff, J. ; Truong, B.
Author_Institution
IBM Corp., Austin, TX, USA
fYear
2004
fDate
25-27 Oct. 2004
Firstpage
173
Lastpage
176
Abstract
This work overviews the interface choices made for the 1:1 on-module buses and the 2:1 off-module buses. Custom circuits used, data recovery methods, signal integrity design and the system verification using register based diagnostics and eye margin mapping. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping are explained.
Keywords
driver circuits; system buses; IBM Power5 bus designs; custom circuits; data recovery methods; eye margin mapping; hardware based verification methods; interface register based diagnostics; off-module buses; on-module buses; signal integrity design; Bandwidth; Clamps; Clocks; Connectors; Design methodology; Driver circuits; History; Registers; Signal design; Signal mapping;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 2004. IEEE 13th Topical Meeting on
Print_ISBN
0-7803-8667-1
Type
conf
DOI
10.1109/EPEP.2004.1407577
Filename
1407577
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