A low-latency software-based route lookup implementation for network processors

Edge and access routers require fast and flexible route table lookup for incoming IP packets at relatively low cost. However, today´s most NPs are not optimized for basic route lookup operations and tend to offload them to expensive TCAM or dedicated search engine. This paper describes a software-based route cache utilizing on-chip SRAM of NP. Accessing high-speed on-chip SRAM instead of long-latency off-chip DRAM can effectively reduce the average search time, eliminating the demand of TCAM and making more headroom for other applications. One of the major design issues is selecting a suitable hash function to make a balance between conflict miss rate and update complexity. The detailed implementation of the program can take advantage of optimized instruction set of NP. Experiments with real-life packet traces show that a high bit rate can be easily achieved with a small SRAM.