• DocumentCode
    430212
  • Title

    Hierarchical multiple associative mapping in cache memories

  • Author

    Zarandi, Hamid R. ; Miremadi, Seyed Ghassem

  • Author_Institution
    Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
  • fYear
    2005
  • fDate
    4-7 April 2005
  • Firstpage
    95
  • Lastpage
    101
  • Abstract
    In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of different sizes. Hence, the length of tag fields associated to each set is also variable and depends on the partition it is in. The proposed mapping function has been simulated with some standard trace files and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping, using LRU replacement policy. Also, its area and power consumption is less than full-associative scheme.
  • Keywords
    cache storage; content-addressable storage; memory architecture; power consumption; LRU replacement policy; cache configuration; cache memory; cache placement scheme; direct mapping; full-associative scheme; hierarchical multiple associative mapping; power consumption; set-associative mapping; Analytical models; Bandwidth; Cache memory; Costs; Energy consumption; High performance computing; Interference; Space technology; Statistical analysis; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Engineering of Computer-Based Systems, 2005. ECBS '05. 12th IEEE International Conference and Workshops on the
  • Print_ISBN
    0-7695-2308-0
  • Type

    conf

  • DOI
    10.1109/ECBS.2005.44
  • Filename
    1409906