DocumentCode :
430230
Title :
Issues and challenges in ramp to production
Author :
Shrimali, Arun ; Venkitachalam, Anand ; Arora, Ravi
Author_Institution :
Texas Instrum. India, India
fYear :
2005
fDate :
21-23 March 2005
Firstpage :
123
Lastpage :
127
Abstract :
As the world is moving toward the deep submicron (DSM) era, understanding silicon behavior is becoming more and more challenging. Models are getting complex and yet not able to reflect the actual silicon behavior. Hence some of the silicon issues cannot be replicated in circuit simulations. The problems found on silicon require the understanding of various tools and techniques available to observe and modify the die. A good understanding of these techniques and debug methodology is required to meet time to market goals. The devices used for mobile applications have stringent power requirements. The devices thus have power conservation modes during which the current drawn is extremely low of the order of tens of microamperes. This paper discusses the challenges and techniques used to identify the issues found in shutdown mode (a power conservation mode), which had to be addressed in order to ramp the device to production.
Keywords :
CMOS integrated circuits; integrated circuit manufacture; power consumption; silicon; time to market; debug methodology; deep submicron technology; mobile applications; power conservation modes; shutdown mode; silicon behavior; time to market; CMOS technology; Circuit simulation; Instruments; Leakage current; Logic design; Logic gates; Production; Silicon; Switches; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
Type :
conf
DOI :
10.1109/ISQED.2005.72
Filename :
1410569
Link To Document :
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