Title :
A technique for designing totally self-checking domino logic circuits
Author :
Tang, C.K. ; Lata, P.K. ; Parkerson, J.P.
Author_Institution :
Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
Abstract :
A scheme for concurrent self-checking domino logic circuit is proposed. The self-checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the self-checking implementation. The scheme is especially suitable for large CMOS domino logic circuits.
Keywords :
CMOS logic circuits; embedded systems; logic design; logic testing; 1-out-of-2 code; CMOS logic circuits; checker circuit; concurrent self-checking domino logic circuit; embedded circuit; inverse function; transistor sharing; CMOS logic circuits; Circuit faults; Electrical fault detection; Encoding; Fault detection; Logic circuits; Logic functions; Logic testing; Monitoring; Very large scale integration;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.14
