Reseeding-based test set embedding with reduced test sequences

A novel technique for reducing the test sequences of reseeding-based schemes is presented in this paper. The proposed technique is generic and can be applied to test set embedding or mixed-mode schemes based on various TPG. The imposed hardware overhead is very small since it is confined to just one extra bit per seed plus one very small counter in the scheme´s control logic, while the test-sequence-length reductions achieved are up to 44.71%. Along with the test-sequence-reduction technique, an efficient seed-selection algorithm for the test-per-clock, LFSR-based, test set embedding case is presented. The proposed algorithm targets the minimization of the selected seed volumes and, combined with the test-sequence-reduction technique, delivers results with fewer seeds and much smaller test sequences than the already proposed approaches.