Title :
Efficient barrier synchronization mechanism for emulated shared memory NOCs
Author_Institution :
VTT Electron., Oulu, Finland
Abstract :
Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming, even in step synchronous emulated shared memory machines (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper, we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.
Keywords :
multi-threading; program control structures; shared memory systems; synchronisation; active memory; arbitrary simultaneous barrier mechanisms; barrier synchronization mechanism; emulated shared memory NOCs; network-on-chip architecture; parallely recursive synchronous MIMD programming; scalable ESMM; step synchronous emulated shared memory machines; thread control; Application software; Computer architecture; Concurrent computing; Frequency synchronization; Network-on-a-chip; Parallel processing; Phase change random access memory; Samarium; Silicon; Yarn;
Conference_Titel :
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN :
0-7803-8558-6
DOI :
10.1109/ISSOC.2004.1411139
