A technique to linearize LDMOS power amplifiers based on derivative superposition and out-of-band impedance optimization

Derivative Superposition @S) has been demonstrated in prior work to improve the linearity performance of a LDMOS power amplifier at power levels far from compression. However, we have found that at higher power levels (close to compression), DS was not effective to provide any linearity improvement. We propose a technique that combines DS with second harmonic impedance tuning which is able to give improvement in linearity much closer to compression point, thus facilitating a higher power efiiciency of the amplifier for a given application. On wafer measurement on a LDMOS device (3x0.8x100pm ) that is optimized with DS and out-of-hand impedance termination shows an improvement in linearity up to 4dB back-offfrom the PldB compression point.