A design of parallel matched filter for path search

In this report, we propose a new architecture of a matched filter used in CDMA systems. The new architecture reduces the calculation cost of data correlation significantly. Since the calculation of the correlation into a matched filter becomes a quite large amount of operation, large circuit scale and high power consumption occur on a mobile system. Accordingly low calculation cost has been demanded. The proposed matched filter applies a two step correlation algorithm into the data processing. Therefore, the amount of the operation can be decreased. In addition, it is expected that the operation speed and the power consumption of a matched filter circuit module are improved.