DocumentCode
430634
Title
On the effectiveness of dynamically allocating resources across program execution phases for media workloads
Author
Banerjee, Subhasis ; Surendra, G. ; Nandy, S.K.
Author_Institution
CAD Lab, Indian Inst. of Sci., Bangalore, India
Volume
1
fYear
2004
fDate
6-9 Dec. 2004
Firstpage
9
Abstract
Processing embedded applications is essentially a trade-off between power and performance. Increasing level of complexity in present day microprocessor at the expense of more power call for different optimization methodologies at architecture level. The study of general characteristics of program execution phases gives insight to dynamically reconfigure or enable/disable additional resources on-demand basis. This leads to significant amount of power saving with negligible or tolerable performance degradation. We characterize execution of such programs into execution phases based on their dynamic IPC profile. We show that program execution of selected phases (based on IPC profile) can be dynamically boosted by activating additional standby functional units which are otherwise powered down for saving energy. Through simulation we show that speedup ranging from 1.1 to 1.25 can be achieved while reducing the energy-delay product (EDP) for most of the media benchmarks evaluated.
Keywords
low-power electronics; message passing; microprocessor chips; optimising compilers; resource allocation; dynamic IPC profile; dynamic resource allocation; dynamic resource reconfiguration; energy-delay product; media workloads; microprocessor; program execution phases; standby functional units activation; Degradation; Electronic mail; Energy consumption; Hardware; Microprocessors; Optimization methods; Power dissipation; Resource management; Runtime; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8660-4
Type
conf
DOI
10.1109/APCCAS.2004.1412678
Filename
1412678
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