Title :
Implementation of half-pel motion estimation IP core for MPEG-4 ASP@L5 texture coding
Author :
Wei-Feng, He ; Zhi-Qiang, Gao ; Zhi-Gang, Mao ; Yan, Zhang
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., China
Abstract :
An efficient fully pipelined parallel 1-D and 2-D mixed motion estimation array architecture for MPEG-4 ASP@L5 encoder is proposed in This work. Unlike most previously presented motion estimation processors, this design can deal with 8× block and 16 × 6 macroblock motion estimation with different searching ranges in full-pel and half-pel resolution. Experimental results show that it is able to estimate half-pel texture motion vectors of MPEG-4 AS Profile in ITU-R601 format in real-time at around 100MHz.
Keywords :
image coding; microprocessor chips; motion estimation; parallel architectures; ITU-R601 format; MPEG-4 ASP@L5 texture coding; fully pipelined motion estimation; half-pel motion estimation IP core; motion estimation processors; parallel array architecture; Application specific processors; Computer architecture; Hardware design languages; Helium; MPEG 4 Standard; Microelectronics; Motion estimation; Process design; Very large scale integration; Video sequences;
Conference_Titel :
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8660-4
DOI :
10.1109/APCCAS.2004.1412714
