A reusable methodology for non-slicing floorplanning

Floorplanning is an important step in an early phase of VLSI design. For faster design convergence, there is an urgent need to start floorplanning as early as possible, even when not all modules are designed. Therefore, it is desirable to consider floorplanning with uncertainty to obtain a compact and reliable floorplan when the dimensions and interconnections of modules are not fully determined. We propose a sequence-pair based floorplanner, named PLP, for uncertain designs.