CMOS RF LNA with high ESD immunity

Author

Tang, Siu-Kei ; Chan, Cheong-Fat ; Choy, Chiu-Sing ; Pun, Kong-Pang

Author_Institution

Dept. of Electron. Eng., Hong Kong Chinese Univ., China

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

321

Abstract

We present a two-stage LNA design with a high ESD immunity. We use a common-gate amplifier as an input stage for our design. The RF input is directly connected to the source of the transistor, which will provide a higher ESD protection than conventional common-source amplifiers. The two-stage LNA is designed to operate at 1.8 GHz with a voltage supply of 1.5 V using AMS 0.35-μm CMOS technology. The new LNA has a measured power gain of 14.1 dB with a noise figure of 5 dB. The reverse isolation is -32 dB, and the output-referred third-order intercept point is 6.3 dBm. The measured HBM ESD withstand voltages are 1.5kV and -3.5kV.

Keywords

CMOS digital integrated circuits; electrostatic discharge; radiofrequency amplifiers; transistors; -3.5 kV; 0.35 micron; 1.5 V; 1.5 kV; 1.8 GHz; 14.1 dB; 32 dB; 5 dB; CMOS RF LNA design; CMOS technology; ESD immunity; HBM ESD; common gate amplifier; output-referred third-order intercept point; transistor; CMOS technology; Electrostatic discharge; Gain measurement; Isolation technology; Noise measurement; Power measurement; Protection; Radio frequency; Radiofrequency amplifiers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412759

Filename

1412759