Low-error carry-free fixed-width multipliers and their application to DCT/IDCT

Author

Tso-Bing Juang ; Shen-Fu Hsiao ; Shiann-Rong Kuang ; Tsai, Ming Yu

Author_Institution

Dept. of Comput. Sci. & Eng., National Sun Yat-sen Univ., Kaohsiung, Taiwan

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

457

Abstract

In this paper, we propose a low-error fixed-width redundant multiplier design. The design is based on the statistical analysis of the value of the truncated partial products in binary signed-digit representation with modified Booth encoding. The overall truncation error is significantly reduced with negligible hardware overhead. Simulation on DCT/IDCT of images with 256 gray levels shows our proposed multiplication design has higher PSNR/SNR.

Keywords

image coding; multiplying circuits; statistical analysis; DCT/IDCT; PSNR/SNR; binary signed-digit representation; carry-free multipliers; fixed-width multipliers; low-error multipliers; modified Booth encoding; multiplication design; multiplier design; redundant multiplier; statistical analysis; truncated partial products; truncation error; Adders; Application software; Circuits; Computer science; Design engineering; Discrete cosine transforms; Encoding; Finite impulse response filter; Finite wordlength effects; Hardware;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412795

Filename

1412795